In recent years, as a substrate for use in a semiconductor package, there has been increasingly used what is called a coreless substrate, which contains no core made of relatively rigid glass epoxy. The coreless substrate includes a build-up substrate (SLC substrate) composed of an insulating layer and patterned conductor layer alternately stacked. A package obtained by mounting a semiconductor chip on the coreless substrate is generally called a coreless package.
FIG. 1 is a cross-sectional view of a conventional coreless package. On a coreless substrate 1, there is mounted a semiconductor chip 3 which electrically connects with an electrode pad (not illustrated) on the surface of the substrate. The space between the surface of the substrate 1 and the semiconductor chip 3 is filled with an underfill 5 made of a resin material. A stiffener 7 made of a resin material is arranged around the semiconductor chip 3 on the substrate 1. The coreless substrate 1, having no rigid core, is lower in stiffness than a substrate with core. The resin stiffener 7 is provided for the purpose of compensating for such low stiffness of the substrate. Referring to FIG. 1, there is further illustrated a ball grid (BGA) 9 for electrically connecting the substrate 1 to another substrate (not illustrated).
In the conventional coreless package of FIG. 1, the effect of resin stiffener is insufficient. Consequently, from the difference of thermal expansion coefficient between the substrate, the semiconductor chip, the underfill and the stiffener, thermal stress is caused by thermal fluctuations in the solder reflow process or the like. The thermal stress may cause defects such as warpage of the entire substrate, occurrence of cracks and fissures in the semiconductor chip, or peeling off of the semiconductor chip from the substrate.
In order to prevent the occurrence of the defects, there is a technique of adding a filler to the resin constituting the stiffener to raise the stiffness of stiffener, or a technique of bringing, by resin component adjustment, the thermal expansion coefficient of stiffener close to the thermal expansion coefficient of silicon constituting the semiconductor chip. However, these conventional techniques are insufficient to supplement the stiffness of substrate to thereby reduce thermal stress.
As another technique, Japanese Published Unexamined Patent Application No. 2003-92376, has disclosed that, in order to increase the mechanical strength of resin stiffener, a reinforcement material (plate) made of iron is buried in the resin stiffener. However, in the technique of this publication, peeling-off may occur in the interface between the resin and reinforcement material (plate) and thus the effect of supplementing the stiffness of substrate to reduce thermal stress may not be achieved. Also, in the technique of this publication, positioning operation for properly arranging a plurality of reinforcement materials (metal pieces) in the resin is needed, thus making the manufacturing process complex.